|本期目录/Table of Contents|

[1]郭希铮,袁佳琦,游小杰,等. 电力电子实时仿真建模的 FPGA 资源优化方法研究[J].电机与控制学报,2020,24(07):12-19.[doi:10.15938/j.emc.2020.07.002]
 GUO Xi-zheng,YUAN Jia-qi,YOU Xiao-jie,et al. Research on FPGA optimization approach of power electronics real-time simulation modeling[J].,2020,24(07):12-19.[doi:10.15938/j.emc.2020.07.002]
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 电力电子实时仿真建模的 FPGA 资源优化方法研究
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《电机与控制学报》[ISSN:1007-449X/CN:23-1 408/TM]

卷:
24
期数:
2020年07
页码:
12-19
栏目:
出版日期:
2020-07-18

文章信息/Info

Title:
 Research on FPGA optimization approach of power electronics real-time simulation modeling
作者:
 郭希铮 袁佳琦 游小杰 张子钰
 (北京交通大学 电气工程学院,北京 100044)
Author(s):
 GUO Xi-zheng YUAN Jia-qi YOU Xiao-jie ZHANG Zi-yu
 (School of Electrical Engineering,BeijingJiaotong University,Beijing,100044,China)
关键词:
实时仿真FPGA资源优化字长仿真步长信噪比
Keywords:
real-time simulation field programmable gate array resource optimization bit-length time step signal-noise ratio
分类号:
TM 464
DOI:
10.15938/j.emc.2020.07.002
文献标志码:
A
摘要:
 如何选择满足建模精度要求的最小字长与仿真步长是电力电子系统实时仿真模型在 FP-GA(field programmable gate array)实现时的难点问题之一。首先,提出了一种电力电子实时仿真建模 FPGA 资源优化方法,该方法基于信噪比理论,通过计算变量字长、仿真步长与模型精度的关系确定满足建模精度要求的最小字长和步长,以此来达到优化 FPGA 资源的效果;然后,以基于 LC 滤波的三相逆变器系统为例,采用 ADC(associated discrete circuit)的方法进行实时仿真建模并计算其信噪比,离线仿真验证了输出字长 25 位,仿真步长 100 ns 是满足模型精度的最小字长和最佳步长;最后,硬件在回路仿真实验和实物实验分别验证了 FPGA 的资源优化效果和建模理论的正确性。
Abstract:
It is one of the most important projects to choose the minimum bit-length and optimal time step which meet model accuracy when real-time simulation model of power electronics is implemented in FP-GA. Based on the concept of SNR (signal-noise ratio),a FPGA resource optimization method was pro-posed for power electronics real-time simulation modeling. The quantitative relationship among time step,bit-length and model accuracy was calculated to choose the minimum bit-length and optimal time step,which can optimize FPGA resource occupation. In addition,taking a three-phase inverter with LC filterfor example,ADC (associated discrete circuit) modeling method was used for real-time simulation mod-eling and the SNR was calculated. Offline simulation verifies that the bit-length for 25 bits and the timestep for 100 ns are the minimum bit-length and optimal time step that meet the model accuracy. Finally,hardware-in-the-loop (HIL) simulation and real experiments verify the effect of FPGA resource optimiza-tion and the validity of modeling method respectively.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2018 -08 -10
基金项目:国家重点研发计划(2016YFE0131700)
作者简介:郭希铮(1980—),男,博士,副教授,研究方向为永磁同步电机控制、电力电子装置等;
            袁佳琦(1994—),女,硕士研究生,研究方向为实时仿真技术;
            游小杰(1964—),男,教授,博士生导师,研究方向为电力电子技术在电力系统中的应用、变频调速技术等;
            张子钰(1994—),女,硕士研究生,研究方向为实时仿真建模。
通信作者:郭希铮
更新日期/Last Update: 2020-09-09